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00023 #ifndef INCLUDED_USRP_STANDARD_H
00024 #define INCLUDED_USRP_STANDARD_H
00025
00026 #include <usrp/usrp_basic.h>
00027 #include <boost/shared_ptr.hpp>
00028 #include <usrp/usrp_tune_result.h>
00029
00030 class usrp_standard_tx;
00031 class usrp_standard_rx;
00032
00033 typedef boost::shared_ptr<usrp_standard_tx> usrp_standard_tx_sptr;
00034 typedef boost::shared_ptr<usrp_standard_rx> usrp_standard_rx_sptr;
00035
00039 class usrp_standard_common
00040 {
00041 int d_fpga_caps;
00042
00043 protected:
00044 usrp_standard_common(usrp_basic *parent);
00045
00046 public:
00052 bool has_rx_halfband() const;
00053
00058 int nddcs() const;
00059
00063 bool has_tx_halfband() const;
00064
00069 int nducs() const;
00070
00080 static void calc_dxc_freq(double target_freq, double baseband_freq, double fs,
00081 double *dxc_freq, bool *inverted);
00082 };
00083
00091 class usrp_standard_rx : public usrp_basic_rx, public usrp_standard_common
00092 {
00093 private:
00094 static const int MAX_CHAN = 4;
00095 unsigned int d_decim_rate;
00096 int d_nchan;
00097 int d_sw_mux;
00098 int d_hw_mux;
00099 double d_rx_freq[MAX_CHAN];
00100
00101 protected:
00102 usrp_standard_rx (int which_board,
00103 unsigned int decim_rate,
00104 int nchan = 1,
00105 int mux = -1,
00106 int mode = 0,
00107 int fusb_block_size = 0,
00108 int fusb_nblocks = 0,
00109 const std::string fpga_filename = "",
00110 const std::string firmware_filename = ""
00111 );
00112
00113 bool write_hw_mux_reg ();
00114
00115 public:
00116
00117 enum {
00118 FPGA_MODE_NORMAL = 0x00,
00119 FPGA_MODE_LOOPBACK = 0x01,
00120 FPGA_MODE_COUNTING = 0x02,
00121 FPGA_MODE_COUNTING_32BIT = 0x04
00122 };
00123
00124 ~usrp_standard_rx ();
00125
00140 static usrp_standard_rx_sptr make(int which_board,
00141 unsigned int decim_rate,
00142 int nchan = 1,
00143 int mux = -1,
00144 int mode = 0,
00145 int fusb_block_size = 0,
00146 int fusb_nblocks = 0,
00147 const std::string fpga_filename = "",
00148 const std::string firmware_filename = ""
00149 );
00156 bool set_decim_rate (unsigned int rate);
00157
00164 bool set_nchannels (int nchannels);
00165
00186 bool set_mux (int mux);
00187
00192 int determine_rx_mux_value(const usrp_subdev_spec &ss);
00193 int determine_rx_mux_value(const usrp_subdev_spec &ss_a, const usrp_subdev_spec &ss_b);
00194
00203 bool set_rx_freq (int channel, double freq);
00204
00208 bool set_fpga_mode (int mode);
00209
00216 bool set_ddc_phase(int channel, int phase);
00217
00246 bool set_format(unsigned int format);
00247
00248 static unsigned int make_format(int width=16, int shift=0,
00249 bool want_q=true, bool bypass_halfband=false);
00250 static int format_width(unsigned int format);
00251 static int format_shift(unsigned int format);
00252 static bool format_want_q(unsigned int format);
00253 static bool format_bypass_halfband(unsigned int format);
00254
00268 bool tune(int chan, db_base_sptr db, double target_freq, usrp_tune_result *result);
00269
00270
00271
00272 unsigned int decim_rate () const;
00273 double rx_freq (int channel) const;
00274 int nchannels () const;
00275 int mux () const;
00276 unsigned int format () const;
00277
00278
00279 bool start ();
00280 bool stop ();
00281 };
00282
00283
00284
00294 class usrp_standard_tx : public usrp_basic_tx, public usrp_standard_common
00295 {
00296 public:
00297 enum coarse_mod_t {
00298 CM_NEG_FDAC_OVER_4,
00299 CM_NEG_FDAC_OVER_8,
00300 CM_OFF,
00301 CM_POS_FDAC_OVER_8,
00302 CM_POS_FDAC_OVER_4
00303 };
00304
00305 protected:
00306 static const int MAX_CHAN = 2;
00307 unsigned int d_interp_rate;
00308 int d_nchan;
00309 int d_sw_mux;
00310 int d_hw_mux;
00311 double d_tx_freq[MAX_CHAN];
00312 coarse_mod_t d_coarse_mod[MAX_CHAN];
00313 unsigned char d_tx_modulator_shadow[MAX_CHAN];
00314
00315 virtual bool set_coarse_modulator (int channel, coarse_mod_t cm);
00316 usrp_standard_tx::coarse_mod_t coarse_modulator (int channel) const;
00317
00318 protected:
00319 usrp_standard_tx (int which_board,
00320 unsigned int interp_rate,
00321 int nchan = 1,
00322 int mux = -1,
00323 int fusb_block_size = 0,
00324 int fusb_nblocks = 0,
00325 const std::string fpga_filename = "",
00326 const std::string firmware_filename = ""
00327 );
00328
00329 bool write_hw_mux_reg ();
00330
00331 public:
00332 ~usrp_standard_tx ();
00333
00347 static usrp_standard_tx_sptr make(int which_board,
00348 unsigned int interp_rate,
00349 int nchan = 1,
00350 int mux = -1,
00351 int fusb_block_size = 0,
00352 int fusb_nblocks = 0,
00353 const std::string fpga_filename = "",
00354 const std::string firmware_filename = ""
00355 );
00356
00363 virtual bool set_interp_rate (unsigned int rate);
00364
00371 bool set_nchannels (int nchannels);
00372
00406 bool set_mux (int mux);
00407
00412 int determine_tx_mux_value(const usrp_subdev_spec &ss);
00413 int determine_tx_mux_value(const usrp_subdev_spec &ss_a, const usrp_subdev_spec &ss_b);
00414
00423 virtual bool set_tx_freq (int channel, double freq);
00424
00425
00426 unsigned int interp_rate () const;
00427 double tx_freq (int channel) const;
00428 int nchannels () const;
00429 int mux () const;
00430
00444 bool tune(int chan, db_base_sptr db, double target_freq, usrp_tune_result *result);
00445
00446
00447
00448 bool start ();
00449 bool stop ();
00450 };
00451
00452 #endif