### this file is sourced not run	
PKGVER=10.2
PKGBUILD=1
PKGARCH=x86_64

# source: james
TARBALL=verilog-$PKGVER.tar.gz
MD5SUM=92078fa508ec25e40d4a9bf73b287720
SRC_URL=ftp://ftp.icarus.com/pub/eda/verilog/v10/$TARBALL
BUNDLE=

SLACKREQ=''
SLACKDESC="iverilog: iverilog $PKGVER (Verilog simulator and synthesis)  
iverilog:  
iverilog: Icarus Verilog is a Verilog simulation and synthesis tool. It 
iverilog: operates as a compiler, compiling source code written in Verilog 
iverilog: (IEEE-1364) into some target format. For batch simulation, the 
iverilog: compiler can generate an intermediate form called vvp assembly. This 
iverilog: intermediate form is executed by the vvp command. For synthesis, 
iverilog: the compiler generates netlists in the desired format.  
iverilog: 
iverilog: http://iverilog.icarus.com/ 
iverilog: 
"
SLACKSUG='qucs'

### default pkg_download
### default pkg_prepare
### default pkg_package
### build
pkg_build() {
	pkg_build_autoconf &&
	pkg_build_slackdesc
}


