! Syntax highlighting patterns for Verilog
!
! INSTALLATION
!
! Load this pattern by starting nedit with:
!
!       nedit -import <name of this file>
!
! Then, check that the patterns were loaded correctly, and choose Save Defaults
! from the Preferences menu.  The new patterns will now be incorporated into
! your own .nedit file, so the next time you start NEdit, you will no longer
! need to use -import.
!
! These comments will not appear in your ~/.nedit
!
nedit.highlightPatterns: VerilogAMS:1:0{\n\
		Comment:"/\\*":"\\*/"::Comment::\n\
		cplus comment:"//":"$"::Comment::\n\
		String Literals:"""":"""":"\\n":String::\n\
		preprocessor line:"^[ ]*`":"$"::Preprocessor::\n\
		Reserved Words:"<(module|endmodule|parameter|begin|end|initial|if|then|else|case|default|endcase|endfunction|for|function|while)>":::Keyword::\n\
		Reserved WordsA:"<(generate|analog|initial_step|cross|final_step|timer|abstol|access|ddt|ddt_nature|discipline|enddiscipline|nature|endnature|exclude|flow|from|idt|idtmod|idt_nature|inf|potential|units|repeat|abs|acos|acosh|asin|asinh|atan|atanh|cos|cosh|exp|ln|log|max|min|pow|sin|sinh|sqrt|tan|tanh|analysis|delay|laplace_nd|laplace_np|laplace_zd|laplace_zp|slew|transition|zi_nd|zi_np|zi_zd|zi_zp)>":::Keyword1::\n\
		Reserved WordsD:"<(specify|endspecify|always|task|endtask|force|release|attribute|case[xz]|endattribute|endprimitive|endtable|forever|primitive|table)>":::Keyword2::\n\
		Predefined Types:"<(and|assign|buf|bufif[01]|cmos|deassign|defparam|disable|edge|event|force|fork|highz[01]|initial|inout|input|integer|join|large|macromodule|medium|nand|negedge|nmos|nor|not|notif[01]|or|output|parameter|pmos|posedge|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif[01]|scalered|signed|small|specparam|strength|strong[01]|supply[01]|time|tran|tranif[01]|tri[01]?|triand|trior|trireg|unsigned|vectored|wait|wand|weak[01]|wire|wreal|wor|xnor|xor)>":::Storage Type::D\n\
		Predefined Disciplines:"<(electrical|logic|voltage|current|magnetic|thermal|kinematic|kinematic_v|rotational|rotational_omega|inout|input|integer|output|parameter|real|strobe|wire)>":::Storage Type1::D\n\
		System Functions:"\\$[a-z_]+":::Subroutine::D\n\
		Numeric Literals:"<([0-9.]*[TGMKkmunpfa]|[0-9]*'[dD][0-9xz\\\\?_]+|[0-9]*'[hH][0-9a-fxz\\\\?_]+|[0-9]*'[oO][0-7xz\\\\?_]+|[0-9]*'[bB][01xz\\\\?_]+|[0-9.]+((e|E)(\\\\+|-)?)?[0-9]*|[0-9]+)>":::Numeric Const::\n\
		Delay Word:"<((#\\(.*\\))|(#[0-9]*))>":::Ada Attributes::D\n\
		Simple Word:"([a-zA-Z][a-zA-Z0-9]*)":::Plain::D\n\
		Instance Declaration:"([a-zA-Z][a-zA-Z0-9_]*)([ \\t]+)([a-zA-Z][a-zA-Z0-9_$]*)([ \\t]*)\\(":::Plain::\n\
		Module name:"\\1":""::Identifier:Instance Declaration:C\n\
		Instance Name:"\\3":""::Identifier1:Instance Declaration:C\n\
		Pins Declaration:"<(\\.([a-zA-Z0-9_]+))>":::Storage Type1::\n\
		Special Chars:"(|,|;|=|&|!|<<|>>|-|/|%|^|~|<|>|!=|<\\+|\\.)":::Keyword::\n\
	}
nedit.languageModes: 	VerilogAMS:.vams::::::
nedit.styles: 	Storage Type1:saddle brown:Bold\n\
 	Keyword1:red3:Bold\n\
 	Keyword2:RoyalBlue3:Bold 
! submitted by Jonathan David 3/12/00 j.david@ieee.org