1/* $NetBSD: hd64570reg.h,v 1.11 2005/12/11 12:21:26 christos Exp $ */
2
3/*
4 * Copyright (c) 1998 Vixie Enterprises
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Vixie Enterprises nor the names
17 * of its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND
21 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR
25 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * This software has been written for Vixie Enterprises by Michael Graff
35 * <explorer@flame.org>. To learn more about Vixie Enterprises, see
36 * ``http://www.vix.com''.
37 */
38
39#ifndef _DEV_IC_HD64570REG_H_
40#define _DEV_IC_HD64570REG_H_
41
42/* XXX
43 * This is really HDLC specific stuff, but...
44 */
45#define CISCO_MULTICAST 0x8f /* Cisco multicast address */
46#define CISCO_UNICAST 0x0f /* Cisco unicast address */
47#define CISCO_KEEPALIVE 0x8035 /* Cisco keepalive protocol */
48#define CISCO_ADDR_REQ 0 /* Cisco address request */
49#define CISCO_ADDR_REPLY 1 /* Cisco address reply */
50#define CISCO_KEEPALIVE_REQ 2 /* Cisco keepalive request */
51
52struct cisco_pkt {
53 u_int32_t type;
54 u_int32_t par1;
55 u_int32_t par2;
56 u_int16_t rel;
57 u_int16_t time0;
58 u_int16_t time1;
59};
60#define CISCO_PKT_LEN 18 /* sizeof doesn't work right... */
61
62#define HDLC_PROTOCOL_IP 0x0800 /* IP */
63#define HDLC_PROTOCOL_IPV6 0x86dd /* IPv6 */
64#define HDLC_PROTOCOL_ISO 0xfefe /* LLC_ISO_LSAP dsap,ssap */
65
66struct hdlc_header {
67 u_int8_t h_addr;
68 u_int8_t h_resv;
69 u_int16_t h_proto;
70};
71#define HDLC_HDRLEN 4
72
73struct hdlc_llc_header {
74 u_int8_t hl_addr;
75 u_int8_t hl_resv;
76 u_int8_t hl_dsap;
77 u_int8_t hl_ssap;
78 u_int8_t hl_ffb; /* cisco: friendly fudge byte */
79};
80
81/*
82 * Hitachi HD64570 defininitions
83 */
84
85/* SCA Control Registers */
86#define SCA_PABR0 2
87#define SCA_PABR1 3
88#define SCA_WCRL 4 /* Wait Control reg */
89#define SCA_WCRM 5 /* Wait Control reg */
90#define SCA_WCRH 6 /* Wait Control reg */
91#define SCA_PCR 8 /* DMA priority control reg */
92
93/* Interrupt registers */
94#define SCA_ISR0 0x10 /* Interrupt status register 0 */
95#define SCA_ISR1 0x11 /* Interrupt status register 1 */
96#define SCA_ISR2 0x12 /* Interrupt status register 2 */
97#define SCA_IER0 0x14 /* Interrupt enable register 0 */
98#define SCA_IER1 0x15 /* Interrupt enable register 1 */
99#define SCA_IER2 0x16 /* Interrupt enable register 2 */
100#define SCA_ITCR 0x18 /* interrupt control register */
101#define SCA_IVR 0x1a /* interrupt vector */
102#define SCA_IMVR 0x1c /* modified interrupt vector */
103
104/* MSCI Channel 0 Registers */
105#define SCA_TRBL0 0x20 /* TX/RX buffer reg */
106#define SCA_TRBH0 0x21 /* TX/RX buffer reg */
107#define SCA_ST00 0x22 /* Status reg 0 */
108#define SCA_ST10 0x23 /* Status reg 1 */
109#define SCA_ST20 0x24 /* Status reg 2 */
110#define SCA_ST30 0x25 /* Status reg 3 */
111#define SCA_FST0 0x26 /* frame Status reg */
112#define SCA_IE00 0x28 /* Interrupt enable reg 0 */
113#define SCA_IE10 0x29 /* Interrupt enable reg 1 */
114#define SCA_IE20 0x2a /* Interrupt enable reg 2 */
115#define SCA_FIE0 0x2b /* Frame Interrupt enable reg */
116#define SCA_CMD0 0x2c /* Command reg */
117#define SCA_MD00 0x2e /* Mode reg 0 */
118#define SCA_MD10 0x2f /* Mode reg 1 */
119#define SCA_MD20 0x30 /* Mode reg 2 */
120#define SCA_CTL0 0x31 /* Control reg */
121#define SCA_SA00 0x32 /* Syn Address reg 0 */
122#define SCA_SA10 0x33 /* Syn Address reg 1 */
123#define SCA_IDL0 0x34 /* Idle register */
124#define SCA_TMC0 0x35 /* Time constant */
125#define SCA_RXS0 0x36 /* RX clock source */
126#define SCA_TXS0 0x37 /* TX clock source */
127#define SCA_TRC00 0x38 /* TX Ready control reg 0 */
128#define SCA_TRC10 0x39 /* TX Ready control reg 1 */
129#define SCA_RRC0 0x3A /* RX Ready control reg */
130
131/* MSCI Channel 1 Registers */
132#define SCA_TRBL1 0x40 /* TX/RX buffer reg */
133#define SCA_TRBH1 0x41 /* TX/RX buffer reg */
134#define SCA_ST01 0x42 /* Status reg 0 */
135#define SCA_ST11 0x43 /* Status reg 1 */
136#define SCA_ST21 0x44 /* Status reg 2 */
137#define SCA_ST31 0x45 /* Status reg 3 */
138#define SCA_FST1 0x46 /* Frame Status reg */
139#define SCA_IE01 0x48 /* Interrupt enable reg 0 */
140#define SCA_IE11 0x49 /* Interrupt enable reg 1 */
141#define SCA_IE21 0x4a /* Interrupt enable reg 2 */
142#define SCA_FIE1 0x4b /* Frame Interrupt enable reg */
143#define SCA_CMD1 0x4c /* Command reg */
144#define SCA_MD01 0x4e /* Mode reg 0 */
145#define SCA_MD11 0x4f /* Mode reg 1 */
146#define SCA_MD21 0x50 /* Mode reg 2 */
147#define SCA_CTL1 0x51 /* Control reg */
148#define SCA_SA01 0x52 /* Syn Address reg 0 */
149#define SCA_SA11 0x53 /* Syn Address reg 1 */
150#define SCA_IDL1 0x54 /* Idle register */
151#define SCA_TMC1 0x55 /* Time constant */
152#define SCA_RXS1 0x56 /* RX clock source */
153#define SCA_TXS1 0x57 /* TX clock source */
154#define SCA_TRC01 0x58 /* TX Ready control reg 0 */
155#define SCA_TRC11 0x59 /* TX Ready control reg 1 */
156#define SCA_RRC1 0x5A /* RX Ready control reg */
157
158
159/* SCA DMA registers */
160
161#define SCA_DMER 0x9 /* DMA Master Enable reg */
162
163/* DMA Channel 0 Registers (MSCI -> memory, or rx) */
164#define SCA_BARL0 0x80 /* buffer address reg */
165#define SCA_BARH0 0x81 /* buffer address reg */
166#define SCA_BARB0 0x82 /* buffer address reg */
167#define SCA_DARL0 0x80 /* Dest. address reg */
168#define SCA_DARH0 0x81 /* Dest. address reg */
169#define SCA_DARB0 0x82 /* Dest. address reg */
170#define SCA_CPB0 0x86 /* Chain pointer base */
171#define SCA_CDAL0 0x88 /* Current descriptor address */
172#define SCA_CDAH0 0x89 /* Current descriptor address */
173#define SCA_EDAL0 0x8A /* Error descriptor address */
174#define SCA_EDAH0 0x8B /* Error descriptor address */
175#define SCA_BFLL0 0x8C /* RX buffer length Low */
176#define SCA_BFLH0 0x8D /* RX buffer length High */
177#define SCA_BCRL0 0x8E /* Byte Count reg */
178#define SCA_BCRH0 0x8F /* Byte Count reg */
179#define SCA_DSR0 0x90 /* DMA Status reg */
180#define SCA_DMR0 0x91 /* DMA Mode reg */
181#define SCA_FCT0 0x93 /* Frame end interrupt Counter */
182#define SCA_DIR0 0x94 /* DMA interrupt enable */
183#define SCA_DCR0 0x95 /* DMA Command reg */
184
185/* DMA Channel 1 Registers (memory -> MSCI, or tx) */
186#define SCA_BARL1 0xA0 /* buffer address reg */
187#define SCA_BARH1 0xA1 /* buffer address reg */
188#define SCA_BARB1 0xA2 /* buffer address reg */
189#define SCA_SARL1 0xA4 /* Source address reg */
190#define SCA_SARH1 0xA5 /* Source address reg */
191#define SCA_SARB1 0xA6 /* Source address reg */
192#define SCA_CPB1 0xA6 /* Chain pointer base */
193#define SCA_CDAL1 0xA8 /* Current descriptor address */
194#define SCA_CDAH1 0xA9 /* Current descriptor address */
195#define SCA_EDAL1 0xAA /* Error descriptor address */
196#define SCA_EDAH1 0xAB /* Error descriptor address */
197#define SCA_BCRL1 0xAE /* Byte Count reg */
198#define SCA_BCRH1 0xAF /* Byte Count reg */
199#define SCA_DSR1 0xB0 /* DMA Status reg */
200#define SCA_DMR1 0xB1 /* DMA Mode reg */
201#define SCA_FCT1 0xB3 /* Frame end interrupt Counter */
202#define SCA_DIR1 0xB4 /* DMA interrupt enable */
203#define SCA_DCR1 0xB5 /* DMA Command reg */
204
205/* DMA Channel 2 Registers (MSCI -> memory) */
206#define SCA_BARL2 0xC0 /* buffer address reg */
207#define SCA_BARH2 0xC1 /* buffer address reg */
208#define SCA_BARB2 0xC2 /* buffer address reg */
209#define SCA_CDAL2 0xC8
210#define SCA_DSR2 0xD0 /* DMA Status reg */
211
212/* DMA Channel 3 Registers (memory -> MSCI) */
213#define SCA_BARL3 0xE0 /* buffer address reg */
214#define SCA_BARH3 0xE1 /* buffer address reg */
215#define SCA_BARB3 0xE2 /* buffer address reg */
216#define SCA_CDAL3 0xE8
217#define SCA_DSR3 0xF0 /* DMA Status reg */
218
219/*
220 * Timer Registers
221 */
222
223/* Timer up-counter */
224#define SCA_TCNTL0 0x60 /* channel 0 */
225#define SCA_TCNTH0 0x61 /* channel 0 */
226#define SCA_TCNTL1 0x68 /* channel 1 */
227#define SCA_TCNTH1 0x69 /* channel 1 */
228#define SCA_TCNTL2 0x70 /* channel 2 */
229#define SCA_TCNTH2 0x71 /* channel 2 */
230#define SCA_TCNTL3 0x78 /* channel 3 */
231#define SCA_TCNTH3 0x79 /* channel 3 */
232
233/* Timer constant register */
234#define SCA_TCONRL0 0x62 /* channel 0 */
235#define SCA_TCONRH0 0x63 /* channel 0 */
236#define SCA_TCONRL1 0x6a /* channel 1 */
237#define SCA_TCONRH1 0x6b /* channel 1 */
238#define SCA_TCONRL2 0x72 /* channel 2 */
239#define SCA_TCONRH2 0x73 /* channel 2 */
240#define SCA_TCONRL3 0x7a /* channel 3 */
241#define SCA_TCONRH3 0x7b /* channel 3 */
242
243/* Timer control/status register */
244#define SCA_TCSR0 0x64 /* channel 0 */
245#define SCA_TCSR1 0x6c /* channel 1 */
246#define SCA_TCSR2 0x74 /* channel 2 */
247#define SCA_TCSR3 0x7c /* channel 3 */
248
249/* Timer expand prescale register */
250#define SCA_TEPR0 0x65 /* channel 0 */
251#define SCA_TEPR1 0x6d /* channel 1 */
252#define SCA_TEPR2 0x75 /* channel 2 */
253#define SCA_TEPR3 0x7d /* channel 3 */
254
255/*
256 * SCA HD64570 Register Definitions
257 */
258
259#define ST3_CTS 8 /* modem input /CTS bit */
260#define ST3_DCD 4 /* modem input /DCD bit */
261
262/*
263 * SCA commands
264 */
265#define SCA_CMD_TXRESET 0x01
266#define SCA_CMD_TXENABLE 0x02
267#define SCA_CMD_TXDISABLE 0x03
268#define SCA_CMD_TXCRCINIT 0x04
269#define SCA_CMD_TXCRCEXCL 0x05
270#define SCA_CMS_TXEOM 0x06
271#define SCA_CMD_TXABORT 0x07
272#define SCA_CMD_MPON 0x08
273#define SCA_CMD_TXBCLEAR 0x09
274
275#define SCA_CMD_RXRESET 0x11
276#define SCA_CMD_RXENABLE 0x12
277#define SCA_CMD_RXDISABLE 0x13
278#define SCA_CMD_RXCRCINIT 0x14
279#define SCA_CMD_RXMSGREJ 0x15
280#define SCA_CMD_MPSEARCH 0x16
281#define SCA_CMD_RXCRCEXCL 0x17
282#define SCA_CMD_RXCRCCALC 0x18
283
284#define SCA_CMD_NOP 0x00
285#define SCA_CMD_RESET 0x21
286#define SCA_CMD_SEARCH 0x31
287
288#define SCA_MD0_CRC_1 0x01
289#define SCA_MD0_CRC_CCITT 0x02
290#define SCA_MD0_CRC_ENABLE 0x04
291#define SCA_MD0_AUTO_ENABLE 0x10
292#define SCA_MD0_MODE_ASYNC 0x00
293#define SCA_MD0_MODE_BYTESYNC1 0x20
294#define SCA_MD0_MODE_BISYNC 0x40
295#define SCA_MD0_MODE_BYTESYNC2 0x60
296#define SCA_MD0_MODE_HDLC 0x80
297
298#define SCA_MD1_NOADDRCHK 0x00
299#define SCA_MD1_SNGLADDR1 0x40
300#define SCA_MD1_SNGLADDR2 0x80
301#define SCA_MD1_DUALADDR 0xC0
302
303#define SCA_MD2_DUPLEX 0x00
304#define SCA_MD2_ECHO 0x01
305#define SCA_MD2_LOOPBACK 0x03
306#define SCA_MD2_ADPLLx8 0x00
307#define SCA_MD2_ADPLLx16 0x08
308#define SCA_MD2_ADPLLx32 0x10
309#define SCA_MD2_NRZ 0x00
310#define SCA_MD2_NRZI 0x20
311#define SCA_MD2_MANCHESTER 0x80
312#define SCA_MD2_FM0 0xC0
313#define SCA_MD2_FM1 0xA0
314
315#define SCA_CTL_RTS_MASK 0x01 /* control state of RTS */
316#define SCA_CTL_RTS_HIGH 0x00 /* raise RTS (low !RTS) */
317#define SCA_CTL_RTS_LOW 0x01 /* lower RTS (raise !RTS) */
318#define SCA_CTL_IDLC_MASK 0x10 /* control idle state */
319#define SCA_CTL_IDLC_MARK 0x00 /* transmit mark in idle state */
320#define SCA_CTL_IDLC_PATTERN 0x10 /* tranmist idle pattern */
321#define SCA_CTL_UDRNC_MASK 0x20 /* control underrun state */
322#define SCA_CTL_UDRNC_AFTER_ABORT 0x00 /* idle after aborting trans */
323#define SCA_CTL_UDRNC_AFTER_FCS 0x20 /* idle after FCS and flag trans */
324
325#define SCA_RXS_DIV_MASK 0x0F /* BRG divisor is 2^(value) */
326#define SCA_RXS_DIV_1 0x00 /* 1 */
327#define SCA_RXS_DIV_2 0x01 /* 2 */
328#define SCA_RXS_DIV_4 0x02 /* 4 */
329#define SCA_RXS_DIV_8 0x03 /* 8 */
330#define SCA_RXS_DIV_16 0x04 /* 16 */
331#define SCA_RXS_DIV_32 0x05 /* 32 */
332#define SCA_RXS_DIV_64 0x06 /* 64 */
333#define SCA_RXS_DIV_128 0x07 /* 128 */
334#define SCA_RXS_DIV_256 0x08 /* 256 */
335#define SCA_RXS_DIV_512 0x09 /* 512 */
336#define SCA_RXS_CLK_MASK 0x70 /* which clock source */
337#define SCA_RXS_CLK_LINE 0x00 /* RXC line input */
338#define SCA_RXS_CLK_LINE_SN 0x20 /* RXC line with noise suppression */
339#define SCA_RXS_CLK_INTERNAL 0x40 /* Baud Rate Gen. output */
340#define SCA_RXS_CLK_ADPLL_OUT 0x60 /* BRG out for ADPLL clock */
341#define SCA_RXS_CLK_ADPLL_IN 0x70 /* line input for ADPLL clock */
342
343#define SCA_TXS_DIV_MASK 0x0F /* BRG divisor is 2^(valud) */
344#define SCA_TXS_DIV_1 0x00 /* 1 */
345#define SCA_TXS_DIV_2 0x01 /* 2 */
346#define SCA_TXS_DIV_4 0x02 /* 4 */
347#define SCA_TXS_DIV_8 0x03 /* 8 */
348#define SCA_TXS_DIV_16 0x04 /* 16 */
349#define SCA_TXS_DIV_32 0x05 /* 32 */
350#define SCA_TXS_DIV_64 0x06 /* 64 */
351#define SCA_TXS_DIV_128 0x07 /* 128 */
352#define SCA_TXS_DIV_256 0x08 /* 256 */
353#define SCA_TXS_DIV_512 0x09 /* 512 */
354#define SCA_TXS_CLK_MASK 0x70 /* which clock source */
355#define SCA_TXS_CLK_LINE 0x00 /* TXC line input */
356#define SCA_TXS_CLK_INTERNAL 0x40 /* Baud Rate Gen. output */
357#define SCA_TXS_CLK_RXCLK 0x60 /* Receive clock */
358
359#define SCA_ST0_RXRDY 0x01
360#define SCA_ST0_TXRDY 0x02
361#define SCA_ST0_RXINT 0x40
362#define SCA_ST0_TXINT 0x80
363
364#define SCA_ST1_IDLST 0x01
365#define SCA_ST1_ABTST 0x02
366#define SCA_ST1_DCDCHG 0x04
367#define SCA_ST1_CTSCHG 0x08
368#define SCA_ST1_FLAG 0x10
369#define SCA_ST1_TXIDL 0x40
370#define SCA_ST1_UDRN 0x80
371
372/* ST2 and FST look the same */
373#define SCA_FST_CRCERR 0x04
374#define SCA_FST_OVRN 0x08
375#define SCA_FST_RESFRM 0x10
376#define SCA_FST_ABRT 0x20
377#define SCA_FST_SHRT 0x40
378#define SCA_FST_EOM 0x80
379
380#define SCA_ST3_RXENA 0x01
381#define SCA_ST3_TXENA 0x02
382#define SCA_ST3_DCD 0x04
383#define SCA_ST3_CTS 0x08
384#define SCA_ST3_ADPLLSRCH 0x10
385#define SCA_ST3_TXDATA 0x20
386
387#define SCA_FIE_EOMFE 0x80
388
389#define SCA_IE0_RXRDY 0x01
390#define SCA_IE0_TXRDY 0x02
391#define SCA_IE0_RXINT 0x40
392#define SCA_IE0_TXINT 0x80
393
394#define SCA_IE1_IDLDE 0x01
395#define SCA_IE1_ABTDE 0x02
396#define SCA_IE1_DCD 0x04
397#define SCA_IE1_CTS 0x08
398#define SCA_IE1_FLAG 0x10
399#define SCA_IE1_IDL 0x40
400#define SCA_IE1_UDRN 0x80
401
402#define SCA_IE2_CRCERR 0x04
403#define SCA_IE2_OVRN 0x08
404#define SCA_IE2_RESFRM 0x10
405#define SCA_IE2_ABRT 0x20
406#define SCA_IE2_SHRT 0x40
407#define SCA_IE2_EOM 0x80
408
409
410/*
411 * Interrupt status register bits
412 */
413#define SCA_ISR0_MSCI_RXRDY0 0x01 /* rx ready port 0 int */
414#define SCA_ISR0_MSCI_TXRDY0 0x02 /* tx ready port 0 int */
415#define SCA_ISR0_MSCI_RXINT0 0x04 /* rx error port 0 int */
416#define SCA_ISR0_MSCI_TXINT0 0x08 /* tx error port 0 int */
417#define SCA_ISR0_MSCI_RXRDY1 0x10 /* rx ready port 1 int */
418#define SCA_ISR0_MSCI_TXRDY1 0x20 /* tx ready port 1 int */
419#define SCA_ISR0_MSCI_RXINT1 0x40 /* rx error port 1 int */
420#define SCA_ISR0_MSCI_TXINT1 0x80 /* tx error port 1 int */
421
422#define SCA_ISR1_DMAC_RX0A 0x01 /* dmac channel 0 int a */
423#define SCA_ISR1_DMAC_RX0B 0x02 /* dmac channel 0 int b */
424#define SCA_ISR1_DMAC_TX0A 0x04 /* dmac channel 1 int a */
425#define SCA_ISR1_DMAC_TX0B 0x08 /* dmac channel 1 int b */
426#define SCA_ISR1_DMAC_RX1A 0x10 /* dmac channel 2 int a */
427#define SCA_ISR1_DMAC_RX1B 0x20 /* dmac channel 2 int b */
428#define SCA_ISR1_DMAC_TX1A 0x40 /* dmac channel 3 int a */
429#define SCA_ISR1_DMAC_TX1B 0x80 /* dmac channel 3 int b */
430
431#define SCA_ISR2_TIMER_IRQ0 0x10 /* timer channel 0 int */
432#define SCA_ISR2_TIMER_IRQ1 0x20 /* timer channel 1 int */
433#define SCA_ISR2_TIMER_IRQ2 0x40 /* timer channel 2 int */
434#define SCA_ISR2_TIMER_IRQ3 0x80 /* timer channel 3 int */
435
436/* masks/values for the Interrupt Control Register (ITCR) */
437#define SCA_ITCR_INTR_PRI_MASK 0x80 /* priority of intrerrupts */
438#define SCA_ITCR_INTR_PRI_MSCI 0x00 /* msci over dmac */
439#define SCA_ITCR_INTR_PRI_DMAC 0x80 /* dmac over msci */
440#define SCA_ITCR_ACK_MASK 0x60 /* mask for intr ack cycle setting */
441#define SCA_ITCR_ACK_NONE 0x00 /* no intr ack cycle */
442#define SCA_ITCR_ACK_SINGLE 0x20 /* single intr ack cycle */
443#define SCA_ITCR_ACK_DOUBLE 0x40 /* double intr ack cycle */
444#define SCA_ITCR_ACK_RESV 0x60 /* reserverd */
445#define SCA_ITCR_VOUT_MASK 0x10 /* vector output */
446#define SCA_ITCR_VOUT_IVR 0x00 /* use IVR */
447#define SCA_ITCR_VOUT_IMVR 0x10 /* use IMVR */
448
449/*
450 * Interrupt enable register bits
451 */
452#define SCA_IER0_MSCI_RXRDY0 0x01 /* enable rx ready port 0 int */
453#define SCA_IER0_MSCI_TXRDY0 0x02 /* enable tx ready port 0 int */
454#define SCA_IER0_MSCI_RXINT0 0x04 /* enable rx error port 0 int */
455#define SCA_IER0_MSCI_TXINT0 0x08 /* enable tx error port 0 int */
456#define SCA_IER0_MSCI_RXRDY1 0x10 /* enable rx ready port 1 int */
457#define SCA_IER0_MSCI_TXRDY1 0x20 /* enable tx ready port 1 int */
458#define SCA_IER0_MSCI_RXINT1 0x40 /* enable rx error port 1 int */
459#define SCA_IER0_MSCI_TXINT1 0x80 /* enable tx error port 1 int */
460
461#define SCA_IER1_DMAC_RX0A 0x01 /* enable dmac channel 0 int a */
462#define SCA_IER1_DMAC_RX0B 0x02 /* enable dmac channel 0 int b */
463#define SCA_IER1_DMAC_TX0A 0x04 /* enable dmac channel 1 int a */
464#define SCA_IER1_DMAC_TX0B 0x08 /* enable dmac channel 1 int b */
465#define SCA_IER1_DMAC_RX1A 0x10 /* enable dmac channel 2 int a */
466#define SCA_IER1_DMAC_RX1B 0x20 /* enable dmac channel 2 int b */
467#define SCA_IER1_DMAC_TX1A 0x40 /* enable dmac channel 3 int a */
468#define SCA_IER1_DMAC_TX1B 0x80 /* enable dmac channel 3 int b */
469
470#define SCA_IER2_TIMER_IRQ0 0x10 /* enable timer channel 0 int */
471#define SCA_IER2_TIMER_IRQ1 0x20 /* enable timer channel 1 int */
472#define SCA_IER2_TIMER_IRQ2 0x40 /* enable timer channel 2 int */
473#define SCA_IER2_TIMER_IRQ3 0x80 /* enable timer channel 3 int */
474
475/* This is for RRC, TRC0 and TRC1. */
476#define SCA_RCR_MASK 0x1F
477
478#define SCA_IE1_
479
480#define SCA_IV_CHAN0 0x00
481#define SCA_IV_CHAN1 0x20
482
483#define SCA_IV_RXRDY 0x04
484#define SCA_IV_TXRDY 0x06
485#define SCA_IV_RXINT 0x08
486#define SCA_IV_TXINT 0x0A
487
488#define SCA_IV_DMACH0 0x00
489#define SCA_IV_DMACH1 0x08
490#define SCA_IV_DMACH2 0x20
491#define SCA_IV_DMACH3 0x28
492
493#define SCA_IV_DMIA 0x14
494#define SCA_IV_DMIB 0x16
495
496#define SCA_IV_TIMER0 0x1C
497#define SCA_IV_TIMER1 0x1E
498#define SCA_IV_TIMER2 0x3C
499#define SCA_IV_TIMER3 0x3E
500
501/*
502 * DMA registers
503 */
504#define SCA_DSR_EOT 0x80
505#define SCA_DSR_EOM 0x40
506#define SCA_DSR_BOF 0x20
507#define SCA_DSR_COF 0x10
508#define SCA_DSR_DE 0x02
509#define SCA_DSR_DEWD 0x01 /* write DISABLE DE bit */
510
511#define SCA_DMR_TMOD 0x10
512#define SCA_DMR_NF 0x04
513#define SCA_DMR_CNTE 0x02
514
515#define SCA_DMER_EN 0x80
516
517#define SCA_DCR_ABRT 0x01
518#define SCA_DCR_FCCLR 0x02 /* Clear frame end intr counter */
519
520#define SCA_DIR_EOT 0x80
521#define SCA_DIR_EOM 0x40
522#define SCA_DIR_BOF 0x20
523#define SCA_DIR_COF 0x10
524
525#define SCA_PCR_BRC 0x10
526#define SCA_PCR_CCC 0x08
527#define SCA_PCR_PR2 0x04
528#define SCA_PCR_PR1 0x02
529#define SCA_PCR_PR0 0x01
530
531/*
532 * Descriptor Status byte bit definitions:
533 *
534 * Bit Receive Status Transmit Status
535 * -------------------------------------------------
536 * 7 EOM EOM
537 * 6 Short Frame ...
538 * 5 Abort ...
539 * 4 Residual bit ...
540 * 3 Overrun ...
541 * 2 CRC ...
542 * 1 ... ...
543 * 0 ... EOT
544 * -------------------------------------------------
545 */
546
547#define ST_EOM 0x80 /* End of frame */
548#define ST_SHRT 0x40 /* Short frame */
549#define ST_ABT 0x20 /* Abort detected */
550#define ST_RBIT 0x10 /* Residual bit detected */
551#define ST_OVRN 0x8 /* Overrun error */
552#define ST_CRCE 0x4 /* CRC Error */
553#define ST_OVFL 0x1 /* Buffer OverFlow error (software defined) */
554
555#define ST_EOT 1 /* End of transmit command */
556
557
558/* DMA Status register (DSR) bit definitions */
559#define DSR_EOT 0x80 /* end of transfer EOT bit */
560#define DSR_EOM 0x40 /* end of frame EOM bit */
561#define DSR_BOF 0x20 /* buffer overflow BOF bit */
562#define DSR_COF 0x10 /* counter overflow COF bit */
563#define DSR_DWE 1 /* write disable DWE bit */
564
565/* MSCI Status register 0 bits */
566
567#define RXRDY_BIT 1 /* RX ready */
568#define TXRDY_BIT 2 /* TX ready */
569
570#define ST3_CTS 8 /* modem input /CTS bit */
571#define ST3_DCD 4 /* modem input /DCD bit */
572
573/*
574 * timer register values
575 */
576#define SCA_TCSR_TME 0x10 /* timer enable */
577#define SCA_TCSR_ECMI 0x40 /* interrupt enable */
578#define SCA_TCSR_CMF 0x80 /* timer complete */
579
580#define SCA_TEPR_DIV_1 0x00 /* 2^(n) prescale divisor */
581#define SCA_TEPR_DIV_2 0x01
582#define SCA_TEPR_DIV_4 0x02
583#define SCA_TEPR_DIV_8 0x03
584#define SCA_TEPR_DIV_16 0x04
585#define SCA_TEPR_DIV_32 0x05
586#define SCA_TEPR_DIV_64 0x06
587#define SCA_TEPR_DIV_128 0x06
588
589
590/* TX and RX Clock Source */
591#define CLK_LINE 0x00 /* TX/RX line input */
592#define CLK_BRG 0x40 /* internal baud rate generator */
593#define CLK_RXC 0x60 /* receive clock */
594
595/* Clocking options */
596#define CLK_INT 0 /* Internal - Baud Rate generator output */
597#define CLK_EXT 1 /* External - both clocks */
598#define CLK_RXCI 2 /* External - Receive Clock only */
599#define CLK_EETC 3 /* EETC clock: TX = int. / RX = ext.*/
600
601#define SCA_DMAC_OFF_0 0x00 /* offset of DMAC for port 0 */
602#define SCA_DMAC_OFF_1 0x40 /* offset of DMAC for port 1 */
603#define SCA_MSCI_OFF_0 0x00 /* offset of MSCI for port 0 */
604#define SCA_MSCI_OFF_1 0x20 /* offset of MSCI for port 1 */
605
606/*
607 * DMA constraints
608 */
609#define SCA_DMA_ALIGNMENT (64 * 1024) /* 64 KB alignment */
610#define SCA_DMA_BOUNDARY (16 * 1024 * 1024) /* 16 MB region */
611
612#endif /* _DEV_IC_HD64570REG_H_ */
613