1/* $NetBSD: hd64570var.h,v 1.11 2012/10/27 17:18:20 chs Exp $ */
2
3/*
4 * Copyright (c) 1999 Christian E. Hopps
5 * Copyright (c) 1998 Vixie Enterprises
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Vixie Enterprises nor the names
18 * of its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND
22 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR
26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * This software has been written for Vixie Enterprises by Michael Graff
36 * <explorer@flame.org>. To learn more about Vixie Enterprises, see
37 * ``http://www.vix.com''.
38 */
39
40#ifndef _DEV_IC_HD64570VAR_H_
41#define _DEV_IC_HD64570VAR_H_
42
43#define SCA_USE_FASTQ /* use a split queue, one for fast traffic */
44
45#define SCA_MTU 1500 /* hard coded */
46
47#ifndef SCA_BSIZE
48#define SCA_BSIZE (SCA_MTU + 4) /* room for HDLC as well */
49#endif
50
51
52struct sca_softc;
53typedef struct sca_port sca_port_t;
54typedef struct sca_desc sca_desc_t;
55
56/*
57 * device DMA descriptor
58 */
59struct sca_desc {
60 u_int16_t sd_chainp; /* chain pointer */
61 u_int16_t sd_bufp; /* buffer pointer (low bits) */
62 u_int8_t sd_hbufp; /* buffer pointer (high bits) */
63 u_int8_t sd_unused0;
64 u_int16_t sd_buflen; /* total length */
65 u_int8_t sd_stat; /* status */
66 u_int8_t sd_unused1;
67};
68#define SCA_DESC_EOT 0x01
69#define SCA_DESC_CRC 0x04
70#define SCA_DESC_OVRN 0x08
71#define SCA_DESC_RESD 0x10
72#define SCA_DESC_ABORT 0x20
73#define SCA_DESC_SHRTFRM 0x40
74#define SCA_DESC_EOM 0x80
75#define SCA_DESC_ERRORS 0x7C
76
77/*
78 * softc structure for each port
79 */
80struct sca_port {
81 u_int msci_off; /* offset for msci address for this port */
82 u_int dmac_off; /* offset of dmac address for this port */
83
84 u_int sp_port;
85
86 /*
87 * CISCO keepalive stuff
88 */
89 u_int32_t cka_lasttx;
90 u_int32_t cka_lastrx;
91
92 /*
93 * clock values, clockrate = sysclock / tmc / 2^div;
94 */
95 u_int8_t sp_eclock; /* enable external clock generate */
96 u_int8_t sp_rxs; /* recv clock source */
97 u_int8_t sp_txs; /* transmit clock source */
98 u_int8_t sp_tmc; /* clock constant */
99
100 /*
101 * start of each important bit of information for transmit and
102 * receive buffers.
103 *
104 * note: for non-DMA the phys and virtual version should be
105 * the same value and should be an _offset_ from the beginning
106 * of mapped memory described by sc_memt/sc_memh.
107 */
108 u_int sp_ntxdesc; /* number of tx descriptors */
109 bus_addr_t sp_txdesc_p; /* paddress of first tx desc */
110 sca_desc_t *sp_txdesc; /* vaddress of first tx desc */
111 bus_addr_t sp_txbuf_p; /* paddress of first tx buffer */
112 u_int8_t *sp_txbuf; /* vaddress of first tx buffer */
113
114 volatile u_int sp_txcur; /* last descriptor in chain */
115 volatile u_int sp_txinuse; /* descriptors in use */
116 volatile u_int sp_txstart; /* start descriptor */
117
118 u_int sp_nrxdesc; /* number of rx descriptors */
119 bus_addr_t sp_rxdesc_p; /* paddress of first rx desc */
120 sca_desc_t *sp_rxdesc; /* vaddress of first rx desc */
121 bus_addr_t sp_rxbuf_p; /* paddress of first rx buffer */
122 u_int8_t *sp_rxbuf; /* vaddress of first rx buffer */
123
124 u_int sp_rxstart; /* index of first descriptor */
125 u_int sp_rxend; /* index of last descriptor */
126
127 struct ifnet sp_if; /* the network information */
128 struct ifqueue linkq; /* link-level packets are high prio */
129#ifdef SCA_USE_FASTQ
130 struct ifqueue fastq; /* interactive packets */
131#endif
132
133 struct sca_softc *sca; /* pointer to parent */
134};
135
136/*
137 * softc structure for the chip itself
138 */
139struct sca_softc {
140 device_t sc_parent; /* our parent device, or NULL */
141 int sc_numports; /* number of ports present */
142 u_int32_t sc_baseclock; /* the base operating clock */
143
144 /*
145 * a callback into the parent, since the SCA chip has no control
146 * over DTR, we have to make a callback into the parent, which
147 * might know about DTR.
148 *
149 * If the function pointer is NULL, no callback is specified.
150 */
151 void *sc_aux;
152 void (*sc_dtr_callback)(void *, int, int);
153 void (*sc_clock_callback)(void *, int, int);
154
155 /* used to read and write the device registers */
156 u_int8_t (*sc_read_1)(struct sca_softc *, u_int);
157 u_int16_t (*sc_read_2)(struct sca_softc *, u_int);
158 void (*sc_write_1)(struct sca_softc *, u_int, u_int8_t);
159 void (*sc_write_2)(struct sca_softc *, u_int, u_int16_t);
160
161 sca_port_t sc_ports[2];
162
163 bus_space_tag_t sc_iot; /* io space for registers */
164 bus_space_handle_t sc_ioh; /* io space for registers */
165
166 int sc_usedma;
167 union {
168 struct {
169 bus_space_tag_t p_memt; /* mem for non-DMA */
170 bus_space_handle_t p_memh; /* mem for non-DMA */
171 bus_space_handle_t p_sca_ioh[16]; /* io for sca regs */
172 bus_size_t p_pagesize; /* memory page size */
173 bus_size_t p_pagemask; /* memory page mask */
174 u_int p_pageshift; /* memory page shift */
175 bus_size_t p_npages; /* num mem pages */
176
177 void (*p_set_page)(struct sca_softc *, bus_addr_t);
178 void (*p_page_on)(struct sca_softc *);
179 void (*p_page_off)(struct sca_softc *);
180 } u_paged;
181 struct {
182 bus_dma_tag_t d_dmat; /* bus DMA tag */
183 bus_dmamap_t d_dmam; /* bus DMA map */
184 bus_dma_segment_t d_seg; /* bus DMA segment */
185 void * d_dma_addr; /* kva of segment */
186 bus_size_t d_allocsize; /* size of region */
187 } u_dma;
188 } sc_u;
189};
190#define scu_memt sc_u.u_paged.p_memt
191#define scu_memh sc_u.u_paged.p_memh
192#define scu_sca_ioh sc_u.u_paged.p_sca_ioh
193#define scu_pagesize sc_u.u_paged.p_pagesize
194#define scu_pagemask sc_u.u_paged.p_pagemask
195#define scu_pageshift sc_u.u_paged.p_pageshift
196#define scu_npages sc_u.u_paged.p_npages
197#define scu_set_page sc_u.u_paged.p_set_page
198#define scu_page_on sc_u.u_paged.p_page_on
199#define scu_page_off sc_u.u_paged.p_page_off
200#define scu_dmat sc_u.u_dma.d_dmat
201#define scu_dmam sc_u.u_dma.d_dmam
202#define scu_seg sc_u.u_dma.d_seg
203#define scu_dma_addr sc_u.u_dma.d_dma_addr
204#define scu_allocsize sc_u.u_dma.d_allocsize
205
206void sca_init(struct sca_softc *);
207void sca_port_attach(struct sca_softc *, u_int);
208int sca_hardintr(struct sca_softc *);
209void sca_shutdown(struct sca_softc *);
210void sca_get_base_clock(struct sca_softc *);
211void sca_print_clock_info(struct sca_softc *);
212
213#endif /* _DEV_IC_HD64570VAR_H_ */
214