1/* $NetBSD: cpufunc.h,v 1.19 2016/01/05 10:20:22 hannken Exp $ */
2
3/*-
4 * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, and by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _X86_CPUFUNC_H_
33#define _X86_CPUFUNC_H_
34
35/*
36 * Functions to provide access to x86-specific instructions.
37 */
38
39#include <sys/cdefs.h>
40#include <sys/types.h>
41
42#include <machine/segments.h>
43#include <machine/specialreg.h>
44
45#ifdef _KERNEL
46
47void x86_pause(void);
48void x86_lfence(void);
49void x86_sfence(void);
50void x86_mfence(void);
51void x86_flush(void);
52#ifndef XEN
53void x86_patch(bool);
54#endif
55void invlpg(vaddr_t);
56void lidt(struct region_descriptor *);
57void lldt(u_short);
58void ltr(u_short);
59void lcr0(u_long);
60u_long rcr0(void);
61void lcr2(vaddr_t);
62vaddr_t rcr2(void);
63void lcr3(vaddr_t);
64vaddr_t rcr3(void);
65void lcr4(vaddr_t);
66vaddr_t rcr4(void);
67void lcr8(vaddr_t);
68vaddr_t rcr8(void);
69void tlbflush(void);
70void tlbflushg(void);
71void dr0(void *, uint32_t, uint32_t, uint32_t);
72vaddr_t rdr6(void);
73void ldr6(vaddr_t);
74void wbinvd(void);
75void breakpoint(void);
76void x86_hlt(void);
77void x86_stihlt(void);
78u_int x86_getss(void);
79
80/* fpu save, restore etc */
81union savefpu;
82void fldcw(const uint16_t *);
83void fnclex(void);
84void fninit(void);
85void fnsave(union savefpu *);
86void fnstcw(uint16_t *);
87uint16_t fngetsw(void);
88void fnstsw(uint16_t *);
89void frstor(const union savefpu *);
90void fwait(void);
91void clts(void);
92void stts(void);
93void fxsave(union savefpu *);
94void fxrstor(const union savefpu *);
95void x86_ldmxcsr(const uint32_t *);
96void x86_stmxcsr(uint32_t *);
97
98void fldummy(void);
99void fp_divide_by_0(void);
100
101/* Extended processor state functions (for AVX registers etc) */
102
103uint64_t rdxcr(uint32_t); /* xgetbv */
104void wrxcr(uint32_t, uint64_t); /* xsetgv */
105
106void xrstor(const union savefpu *, uint64_t);
107void xsave(union savefpu *, uint64_t);
108void xsaveopt(union savefpu *, uint64_t);
109
110void x86_monitor(const void *, uint32_t, uint32_t);
111void x86_mwait(uint32_t, uint32_t);
112/* x86_cpuid2() writes four 32bit values, %eax, %ebx, %ecx and %edx */
113#define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
114void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
115
116/* Use read_psl, write_psl when saving and restoring interrupt state. */
117void x86_disable_intr(void);
118void x86_enable_intr(void);
119u_long x86_read_psl(void);
120void x86_write_psl(u_long);
121
122/* Use read_flags, write_flags to adjust other members of %eflags. */
123u_long x86_read_flags(void);
124void x86_write_flags(u_long);
125
126void x86_reset(void);
127
128/*
129 * Some of the undocumented AMD64 MSRs need a 'passcode' to access.
130 *
131 * See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
132 */
133
134#define OPTERON_MSR_PASSCODE 0x9c5a203aU
135
136uint64_t rdmsr(u_int);
137uint64_t rdmsr_locked(u_int);
138int rdmsr_safe(u_int, uint64_t *);
139uint64_t rdtsc(void);
140uint64_t rdpmc(u_int);
141void wrmsr(u_int, uint64_t);
142void wrmsr_locked(u_int, uint64_t);
143void setfs(int);
144void setusergs(int);
145
146#endif /* _KERNEL */
147
148#endif /* !_X86_CPUFUNC_H_ */
149